1. Field of the Invention
The present invention relates to a source drive amplifier of a liquid crystal display and, more particularly, to a source drive amplifier used in, for example, the driving circuit of a thin film transistor liquid crystal display.
2. Description of Related Art
The thin film transistor liquid crystal display (TFT LCD) is known as an active array type display. The array is composed of a plurality of pixels (or dots), each having a driving electrode and a common electrode commonly used with the other pixels. The LCD is driven by an AC (alternative current) signal. That is, if the voltage applied to the driving electrode is positive with respect to that of the common electrode when the first frame is displayed, the voltage applied to the driving electrode is negative with respect to that of the common electrode in the next frame.
Under the consideration of the difference of the common electrodes and the image quality, there are two well-known driving methods provided: dot inversion driving and row inversion driving. In the dot inversion driving system, if the odd dots of the odd lines of the first frame are driven by a positive voltage with respect to the common electrode, the even dots of the odd lines of the first frame are driven by a negative voltage with respect to the common electrode. The odd dots of the even lines of the first frame are driven by a negative voltage with respect to the common electrode, and the even dots are driven by a positive voltage with respect to the common electrode.
Then, the odd dots of the odd lines of the second frame are driven by a negative voltage with respect to the common electrode, and the even dots are driven by a positive voltage with respect to the common electrode. Meanwhile, the odd points of the even lines of the second frame are driven by a positive voltage with respect to the common electrode, and the even points are driven by a negative voltage with respect to the common electrode.
In the row inversion system, if all dots of the odd lines of the first frame are driven by a positive voltage with respect to the common electrode, all the dots of the even lines of the first frame will be driven by a negative voltage with respect to the common electrode. Then, all dots of the odd lines of the second frame are driven by a negative voltage with respect to the common electrode, and all dots of the even lines of the second frame are driven by a positive voltage with respect to the common electrode.
FIG. 5 is a schematic view showing the driving structure of an active thin film liquid crystal display with K columns by L rows. As shown in the figure, If there are K pixels 901 in the horizontal direction, K channels of source drive units (SDUs) are required for driving. In the vertical direction, a gate driver 903 is employed to drive the voltages of the pixels 901 on each scanning line 904 sequentially for being sampled and hold on the driving electrode of each pixel 901.
FIG. 6 is a circuit diagram of the source drive unit 902 of an active thin film liquid crystal display, which has a multiplex (MUX) 911 controlled by a polarity switching signal PN for switching the output of a positive digital to analog converter 912 (P-DAC) or negative digital to analog converter 913 (N-DAC) to a voltage follower formed by an operational amplifier 914, thereby amplifying the driving ability to generate a driving output DRVO. The driving output DRVO is then entered to a CMOS transmission gate 915 controlled by an output enable signal (OE) to output a driving voltage VLCD to the column of the panel of a thin film transistor liquid crystal display. The operating waveforms are illustrated in FIG. 7, wherein the P-DAC 912 and N-DAC 913 are controlled by an input digital data so as to generate a driving voltage required by a respective illumination. The outputs of the P-DAC 912 and N-DAC 913 are similar, but symmetric with respect to the common electrode, so as to satisfy the AC driving requirement.
To save power, the output voltages of the P-DAC 912 and Nxe2x88x92 DAC 913 are generally in the range from VSS+0.1V to VDDxe2x88x920.1V. Therefore, the operational amplifier used in the source drive unit 902 must have the capability of fill rail-to-rail. Moreover, when the output is higher than the voltage of the common electrode, a large current source out is required so that the load capacitor (primarily the layout strayed capacitor on the panel of the thin film transistor liquid crystal display) is charged rapidly to a high voltage. Moreover, when the output is lower than the voltage of the common electrode, a large current sink capability is required for discharging the high voltage of the load capacitor of the thin film transistor liquid crystal display to a driving low voltage.
To match this requirement, the circuit of an operational amplifier used in a conventional source drive unit is disclosed as shown in FIG. 8, which is a full rail-to-rail AB class operational amplifier (a detailed description of such can be found in U.S. Pat. No. 6,100,762). The operational amplifier includes a first differential amplifier formed by an NMOS pair (N1, N2) and a second differential amplifier formed by a PMOS pair (P1, P2). The two differential amplifiers are connected in parallel for being used as an input. The output currents of the two differential amplifiers are summed via a current mirror circuit (N5_N6, N7_N8, P5_P6), and outputted at node A to drive the AB class amplifier formed by transistors N9, N10, N12, N13, N14, P10, P11, and P12) for being used as the output of the operational amplifier, so as to acquire a large current source out and sink in capabilities.
The aforesaid conventional operational amplifier suffers a disadvantage in having a very large DC offset. Such a disadvantage is encountered because the threshold voltages (VTH) of different MOS devices may be varied from xc2x1 several mV to xc2x1 several tens of mV, in the CMOS manufacturing process. Moreover, in the full rail-to-rail AB class amplifier, the DC offset caused by VTH is particularly serious, which is analyzed as follows:                     when        ⁢                  xe2x80x83                ⁢                  V                      i            ⁢                          xe2x80x83                        ⁢            n                               less than               V        TH_N1              ,          
        ⁢                  V        OS_L            =                                                                                                        gm                    P1                                    ⁢                  Δ                  ⁢                                      xe2x80x83                                    ⁢                                      V                    TH_P1P2                                                  +                                                      gm                    N5                                    ⁢                  Δ                  ⁢                                      xe2x80x83                                    ⁢                                      V                    TH_N5N6                                                  +                                                      gm                    N7                                    ⁢                  Δ                  ⁢                                      xe2x80x83                                    ⁢                                      V                    TH_N7N8                                                  +                                                                                                          gm                  P5_L                                ⁢                Δ                ⁢                                  xe2x80x83                                ⁢                                  V                  TH_P5P6                                                                              gm          P1                                        when        ⁢                  xe2x80x83                ⁢                  V          TH_N1                     less than               V                  i          ⁢                      xe2x80x83                    ⁢          n                     less than               (                              V            DD                    -                      V            TH_P1                          )              ,          
        ⁢                  V        OS_M            =                                                                                                        gm                    P1                                    ⁢                  Δ                  ⁢                                      xe2x80x83                                    ⁢                                      V                    TH_P1P2                                                  +                                                      gm                    N1                                    ⁢                  Δ                  ⁢                                      xe2x80x83                                    ⁢                                      V                    TH_N1N2                                                  +                                                      gm                    N5                                    ⁢                  Δ                  ⁢                                      xe2x80x83                                    ⁢                                      V                    TH_N5N6                                                  +                                                                                                                              gm                    N7                                    ⁢                  Δ                  ⁢                                      xe2x80x83                                    ⁢                                      V                    TH_N7N8                                                  +                                                      gm                    P5_M                                    ⁢                  Δ                  ⁢                                      xe2x80x83                                    ⁢                                      V                    TH_P5P6                                                                                                            gm            P1                    +                      gm            N1                                                  when        ⁢                  xe2x80x83                ⁢                  (                                    V              DD                        -                          V              TH_P1                                )                     less than               V                  i          ⁢                      xe2x80x83                    ⁢          n                      ,          
        ⁢                            V          OS_H                =                                                            gm                N1                            ⁢              Δ              ⁢                              xe2x80x83                            ⁢                              V                TH_N1N2                                      +                                          gm                P5_H                            ⁢              Δ              ⁢                              xe2x80x83                            ⁢                              V                TH_P5P6                                                          gm            N1                              ;      
wherein gmPt, gmNj represent the transfer-conductance of PMOS transistor (Pi, i=1, 2, 3 . . . ), and the transfer-conductance of NMOS transistor (Nj, j=1, 2, 3 . . . ); the gmP5xe2x80x94H gmP5xe2x80x94M, gmP5xe2x80x94L are different from each other due to conducting current; xcex94VTHxe2x80x94N1N2 represents the difference of the voltage threshold between the NMOS differential pair N1 and N2. Other differential pairs or current mirror pairs are represented by same symbols.
In practical, in the middle voltage section VTHxe2x80x94N1 less than Vin less than (VDDxe2x88x92VTHxe2x80x94PI); this AB class operational amplifier generally has a DC offset as high as xc2x115 mV, or even xc2x120 mV, and when in a low voltage, Vin less than VTHxe2x80x94N1, the DC offset is as high as xc2x140 mV.
An active thin film transistor liquid crystal display may use several thousand channels of source drive units. If such a large DC offset is existed in each channel, it implies that the voltage driven to each pixel has different constant error, which will cause a bad uniformity in display.
Besides, the gain of this AB class operational amplifier is very large. Such a large gain and the strayed capacitor in the node B of FIG. 8 will introduce an inductance in the output impedance. This inductance will resonate with the capacitor of the liquid crystal display to generate a peak gain. Thus, the gain margin of the amplifier will be insufficient, and an oscillation is likely to occur. To avoid the oscillation, the compensation capacitor CC must be enlarged, but this will decrease the bandwidth of the amplifier. As a result, the voltage skew rate is insufficient and the load of the liquid crystal display can not be driven in a high speed. Therefore, the NMOS transistor N4 and PMOS transistor P4 are necessary to be used for turbo bias, so as to provide a common mode positive feedback to speed up the voltage variation rate. However, as shown in FIG. 9, after adding common mode positive feedback, a large overshoot will be encountered in the front edge of the waveform. The voltage can be sampled and hold in the driving electrode of the LCD only after the overshoot disappears. Therefore, the driving speed is still restricted.
In the operational amplifier disclosed in Japan Patent Publication No. 09-018253, a source drive unit uses half of the A class amplifiers with NMOS differential inputs as a source amplifier to provide a large current source out capability, and uses half of A class amplifiers with PMOS differential inputs as a sink amplifier. The input of the source amplifier is always connected to the P-DAC and the input of the sink amplifier is always connected to the N-DAC.
Although the aforesaid circuit structure may provide a low DC offset, the source amplifier has only powerful source out capability, while the pull down capability is only of several xcexcA. Therefore, when the output driving voltage of a scanning line is much lower than that of the previous one, a very long time is necessary for pulling down the driving voltage to a required voltage (which is still larger than the voltage of a common electrode). Similarly, the sink amplifier also has the problem of slow pull high. Therefore, the system must perform an extra potential reset operation. That is, a CMOS transmission gate must be used between two lines for quickly charging and discharging the load capacitance of the liquid crystal display to a voltage of the common electrode. This will increase the complex of the circuit and control signals. The more worse is that several are necessary for performing potential reset operation and thus, the driving speed will be restricted.
In addition, only one half of the amplifiers in the driver of the aforesaid circuit structure have a large current source out capability, while another half has only a current source out capability of several xcexcA. Therefore, it can not be used in the row inversion driving scheme because, in row inversion driving, all the pixels of the line are driven by the positive voltage with respect to the common electrode or by the negative voltage with respect to the common electrode. Consequently, the use thereof is restricted and thus, it is desired for the above conventional circuit to be improved.
The object of the present invention is to provide a source drive amplifier of a liquid crystal display for effectively eliminating the DC offset problem. The present source drive amplifier can be used in the dot inversion system and row inversion system without the need of potential reset.
To achieve the object, the source drive amplifier of a liquid crystal display in accordance with the present invention, comprises: a first input circuit controlled by a polarity switching signal for being selectively switched into an NMOS differential amplifying circuit and a bias circuit; a second input circuit controlled by a polarity switching signal for being selectively switched into a bias circuit and a PMOS differential amplifying circuit, wherein, when the polarity switching signal is in a first state, the first and second input circuits are switched into an NMOS differential amplifying circuit and a bias circuit, respectively, and when the polarity switching signal is in a second state, the first and second input circuits are switched into a bias circuit and a PMOS differential amplifying circuit; and, an output transistor pair having an NMOS transistor and a PMOS transistor, wherein, an output of the first input circuit switched into an NMOS differential amplifying circuit drives the PMOS transistor of the output transistor pair for being used as a source out amplifying output stage, and a current provided by the NMOS transistor is used as a bias; and an output of the second output circuit switched into a PMOS differential amplifying circuit drives the NMOS transistor of the output transistor pair for being used as a sink in amplifying output stage, and a current provided by the PMOS transistor is used as a bias.
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.